Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD”, “programmable logic device”, and “programmable integrated circuit” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example, FIG. 1 illustrates an FPGA architecture 100 that includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs 101), configurable logic blocks (CLBs 102), random access memory blocks (BRAMs 103), input/output blocks (IOBs 104), configuration and clocking logic (CONFIG/CLOCKS 105), digital signal processing blocks (DSPs 106), specialized input/output blocks (I/O 107) (e.g., configuration ports and clock ports), and other programmable logic 108 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (PROC 110).
In some FPGAs, each programmable tile includes a programmable interconnect element (INT 111) having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element (INT 111) also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of FIG. 1.
For example, a CLB 102 can include a configurable logic element (CLE 112) that can be programmed to implement user logic plus a single programmable interconnect element (INT 111). A BRAM 103 can include a BRAM logic element (BRL 113) in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. A DSP tile 106 can include a DSP logic element (DSPL 114) in addition to an appropriate number of programmable interconnect elements. An IOB 104 can include, for example, two instances of an input/output logic element (IOL 115) in addition to one instance of the programmable interconnect element (INT 111). As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 115 are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element 115.
In the pictured embodiment, a columnar area near the center of the die (shown shaded in FIG. 1) is used for configuration, clock, and other control logic. Horizontal areas 109 extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.
Some FPGAs utilizing the architecture illustrated in FIG. 1 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block PROC 110 shown in FIG. 1 spans several columns of CLBs and BRAMs.
Note that FIG. 1 is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of FIG. 1 are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB columns varies with the overall size of the FPGA.
For many FPGA devices, such as FPGA 100 of FIG. 1, core logic elements such as CLBs 102 are powered by a main voltage supply (VDD), I/O circuitry such as IOBs 104 are powered by a separate auxiliary voltage supply (VCCAUX), where VCCAUX is typically greater than VDD, and the configuration memory cells are powered by a regulated voltage (Vgg) that is typically generated using a well-known bandgap reference voltage (Vbg_ref). In some FPGAs, for example, VDD has a voltage of between approximately 1.0-1.2 volts, VCCAUX has a voltage of approximately 2.5 volts, and Vgg is typically regulated to approximately one transistor threshold voltage (VT) above VDD (e.g., to between approximately 1.3-1.5 volts).
For example, FIG. 2 shows a simplified portion 200 of FPGA 100 that includes a bandgap reference voltage circuit 205, a VCCAUX voltage regulator circuit 210, a plurality of configuration memory cells 230, I/O circuitry 250, and core logic 260. Voltage regulator 210, which includes a PMOS transistor 211 and an operational amplifier (op-amp) 212, generates a regulated voltage Vgg at a power node A for powering memory cells 230, which store configuration bits (CB) that may be provided to control various configurable elements within I/O circuitry 250 and core logic 260 via signal lines 231A and 231B, respectively, which are shown collectively in FIG. 2 for simplicity. (Note that in the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals and voltages.)
In VCCAUX voltage regulator circuit 210, PMOS transistor 211 is coupled between auxiliary voltage supply VCCAUX and node A, and has a well region tied to VCCAUX. Operational amplifier 212, which is well-known, includes a first input terminal coupled to receive a bandgap reference voltage Vbg_ref from bandgap reference voltage circuit 205, a second input terminal coupled to node A, and an output terminal coupled to the gate of PMOS transistor 211. Bandgap reference voltage circuit 205 can generate a value of Vbg_ref that is relatively insensitive to process and temperature variations, for example, so that configuration memory cells 230 which store logic high values of CB drive signal lines 231 with a CB signal having a voltage approximately equal to a specified value of Vgg, irrespective of the operating temperature.
FIG. 3 shows a programmable interconnect point (PIP) 300 that can be included, for example, in the programmable interconnect element 111 shown in FIG. 1. PIP 300 includes an NMOS pass transistor 310 and a configuration memory cell 230. NMOS pass transistor 310 is coupled between interconnect signal lines 303A and 303B, and has a gate terminal coupled to memory cell 230 via signal line 231. Memory cell 230 stores a CB that controls operation of NMOS pass transistor 310, and although not shown for simplicity in FIG. 3, includes a power terminal coupled to receive regulated voltage Vgg. CB is typically loaded into memory cell 230 during configuration of FPGA 100. During normal operation of FPGA 100, a logic high value of CB (e.g., CB≈Vgg) turns on transistor 310 and connects signal lines 303A-303B together, and conversely, a logic low value of CB (e.g., CB≈0 volts) turns off transistor 310 and isolates signal lines 303A-303B from each other. As mentioned above, regulated voltage Vgg is typically regulated to approximately one transistor threshold voltage VT above VDD. Because the voltage swing of logic signals on signal lines 303A-303B is typically between 0 volts and VDD, driving the gate of NMOS transistor 310 with a value of regulated voltage Vgg that is approximately one transistor threshold voltage VT greater than VDD allows NMOS transistor 310 to pass a logic high signal without a VT drop across transistor 310.
FIG. 4 illustrates a voltage supply circuit 400 in an exemplary FPGA, e.g., the FPGA of FIG. 2. Voltage supply circuit 400 includes bandgap circuit 410, regulator circuit 420, start-up circuit 430, and NMOS transistor MN2, and provides regulated voltage Vgg to memory cells 230 via regulated voltage node 440. Bandgap circuit 410 generates bandgap reference voltage Vbg_ref and supplies the bandgap reference voltage Vbg_ref to voltage regulator circuit 420, where Vbg_ref drives one input terminal of operational amplifier 422. The other input terminal of operational amplifier 422 is driven by regulated voltage node 440, and the output terminal of operational amplifier 422 provides pass voltage Vgg_pass. Note that some known voltage supply circuits include a resistor divider (not shown, but see FIG. 10) on the feedback path between regulated voltage node 440 and operational amplifier 422, while in other voltage supply circuits the reference voltage Vbg_ref is brought up to the Vgg voltage level. Regulator circuit 420 also includes PMOS pull-up transistors MP1 and MP2, coupled in series between auxiliary voltage supply VCCAUX and regulated voltage node 440. The gate terminal of PMOS transistor MP1 is coupled to receive pass voltage Vgg_pass. The gate terminal of PMOS transistor MP2 is coupled to receive a power down signal PDNB, inverted by inverter 421. The bodies of PMOS transistors MP1 and MP2 are coupled to VCCAUX, e.g., through well biasing.
Start-up circuit 430 includes PMOS transistor MP3 and NMOS transistor MN1. PMOS transistor MP3 and NMOS transistor MN1 are coupled in series between VCCAUX and regulated voltage node 440, with the gate of PMOS transistor MP3 coupled to ground GND and the gate of NMOS transistor MN1 receiving a voltage clamp signal CLMP.
NMOS transistor MN2 is a diode-connected transistor coupled between regulated voltage node 440 and ground GND, and provides current for a closed loop phase margin, as is described in more detail below.
For simplicity, FIG. 4 omits the one or more well-known unity-gain buffers that may be coupled between the output of operational amplifier 422 and the gate of transistor MP1. In addition, although not shown for simplicity, bandgap reference voltage Vbg_ref may be provided to a plurality of regulator circuits 420 and start-up circuits 430 distributed across the integrated circuit. Also not shown for simplicity, a single operational amplifier 422 can be used to drive many pull-up transistors MP1 and MP2, if desired.
Voltage supply circuit 400 functions as follows. During operation of the integrated circuit, bandgap circuit 410 provides a bandgap reference voltage Vbg_ref, using any of many known methods. Operational amplifier 422 is well known, and generates a value for pass voltage Vgg_pass that results in a negligible voltage differential between its input terminals, thereby maintaining the regulated voltage Vgg approximately equal to the voltage of bandgap reference voltage Vbg_ref. Pass voltage Vgg_pass, which controls the conductivity of PMOS transistor MP1, is adjusted by operational amplifier 422 so that the current provided by MP1 pulls up the voltage of regulated voltage Vgg in response to dips in Vgg caused by leakage current in memory cells 230 and/or current from transistor MN2. (Note that power down signal PDNB is high while the integrated circuit is operating, so the output of inverter 421 is low and PMOS transistor MP2 is on.) In this manner, the dynamic current provided by PMOS transistor MP1 compensates for leakage current in memory cells 230 to maintain the regulated voltage Vgg at the desired voltage level (e.g., Vbg_ref).
Start-up circuit 430, which is well-known, is primarily used during device power-up operations. For example, upon device power-on, voltage clamp signal CLMP is driven to a positive voltage that turns on transistor MN1 to quickly charge regulated voltage Vgg until Vgg reaches a level that causes transistor MN1 to turn off, for example, when regulated voltage Vgg becomes greater than one threshold voltage VT below the voltage of voltage clamp signal CLMP. In this manner, when operational amplifier 422 becomes operational, the reference voltage Vgg is sufficient to allow operational amplifier 422 to operate normally (i.e., to avoid overshoot conditions).
An important characteristic of voltage supply circuits is the value of the phase margin. As shown in FIG. 4, voltage supply circuits have the inherent characteristic that the regulated voltage Vgg is controlled using negative feedback. In other words, the voltage supply circuit includes a loop, which in the circuit of FIG. 4 includes the path through operational amplifier 422, via pass voltage Vgg_pass to PMOS transistor MP1, and back to operational amplifier 422 via PMOS transistor MP2 and regulated voltage node 440. In adverse conditions (e.g., in high temperatures, or in an integrated circuit manufactured at the fast process corner) such a loop can begin to oscillate. If the phase margin of the circuit is sufficiently large, the oscillation will die out. If the phase margin of the circuit is too small, the loop will continue to oscillate and the integrated circuit will not function properly. Therefore, it is desirable to increase the phase margin of a voltage supply circuit.
A reduction in the phase margin of a voltage regulator circuit can have many causes. For example, a variation in temperature can cause a reduction in phase margin. Further, an integrated circuit manufactured in one corner of the fabrication process can have a lower phase margin that an otherwise identical integrated circuit manufactured at a different process corner. The size of NMOS transistor MP1 is typically selected to handle the leakage current under worst-case conditions, plus a margin of error, typically resulting in an over-design of transistor strength. The larger size of transistor MP1 increases the loop gain of the circuit, which further reduces the phase margin.
One known method of increasing the phase margin is illustrated in FIG. 4. The addition of a diode to ground (e.g., NMOS transistor MN2, coupled as shown in FIG. 4) can increase the phase margin by providing for additional leakage current between regulated voltage Vgg and ground GND. This additional leakage current makes the current requirements more predictable across temperature and process variations, by increasing the current requirements for all of the integrated circuits. Because the current requirements are more predictable, regulator circuit 420 can be better designed (e.g., transistor MP1 can be properly sized) to provide a consistent phase margin across temperature and process variations. However, the addition of such “leaker circuits” (e.g., transistor MN2) increases the power consumption of the integrated circuit. Further, this approach is of limited value, because it does not address the increase in loop gain caused by the increasing loads as integrated circuits increase in size.
Therefore, it is desirable to provide additional circuits and methods of increasing the phase margin of a supply voltage circuit in an integrated circuit.